Package structure and manufacturing method thereof

ABSTRACT

A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of U.S. ProvisionalApplication No. 63/088,422, filed on Oct. 6, 2020. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND Technical Field

The disclosure relates to a semiconductor structure and a manufacturingmethod thereof, and particularly relates to a package structure and amanufacturing method thereof.

Description of Related Art

The key to heterogeneous chiplet integration is the electricalconnection between two chips. At present, Intel uses the embeddedmulti-die interconnect bridge (EMIB) to connect two chips, so as toachieve partial or local high-density interconnection. However, theissue encountered by the technology is that a bridge must be embedded inan organic substrate through the lamination technology, so the surfaceneeds to be flat enough to perform the subsequent flip-chip packaging ofthe chips.

SUMMARY

The disclosure provides a package structure, which has better structuralreliability, especially a flat surface for flip chip bonding.

The disclosure also provides a manufacturing method of a packagestructure, which is used to manufacture the package structure.

The package structure of the disclosure includes a bridge, aninterposer, a first redistribution structure layer, a secondredistribution structure layer, and multiple chips. The bridge includesa silicon substrate, a redistribution circuit layer, and multiple bridgepads. The redistribution circuit layer is disposed on the siliconsubstrate. The bridge pads are disposed on the redistribution circuitlayer and are electrically connected to the redistribution circuitlayer. The interposer includes an intermediate layer, multipleconductive vias, multiple first pads, and multiple second pads. Theintermediate layer has an upper surface and a lower surface opposite toeach other. The conductive vias penetrate the intermediate layer and arerespectively connected to the first pads located on the upper surfaceand the second pads located on the lower surface. The bridge is embeddedin the intermediate layer and the bridge pads are aligned with the uppersurface. The first redistribution structure layer is disposed on theupper surface of the interposer and is electrically connected to thefirst pads and the bridge pads of the bridge. The second redistributionstructure layer is disposed on the lower surface of the interposer andis electrically connected to the second pads. The chips are disposed onthe first redistribution structure layer and are electrically connectedto the first redistribution structure layer. The chips are electricallyconnected to each other through the bridge.

In an embodiment of the disclosure, the package structure furtherincludes a multiple chip pads, which are disposed on the firstredistribution structure layer and are electrically connected to thefirst redistribution structure layer. The chips are electricallyconnected to the first redistribution structure layer and the bridgethrough the chip pads.

In an embodiment of the disclosure, the package structure furtherincludes multiple copper pillars, multiple solders, and multiple solderballs. The copper pillars are respectively disposed on the chips. Thesolders are respectively disposed on the copper pillars. The copperpillars are respectively located between the chips and the solders. Thechips are electrically connected to the bridge through the copperpillars and the solders. The solder balls are disposed on the chips. Thechips are electrically connected to the first redistribution structurelayer through the solder balls.

In an embodiment of the disclosure, the package structure furtherincludes multiple solder ball pads and multiple solder balls. The solderball pads are disposed on the second redistribution structure layer andare electrically connected to the second redistribution structure layer.The solder balls are respectively disposed on the solder ball pads.

The manufacturing method of the package structure of the disclosureincludes the following steps. A bridge is provided. The bridge includesa silicon substrate, a redistribution circuit layer, and multiple bridgepads. The redistribution circuit layer is disposed on the siliconsubstrate. The bridge pads are disposed on the redistribution circuitlayer and are electrically connected to the redistribution circuitlayer. The bridge is embedded in an interposer. The interposer includesan intermediate layer, multiple conductive vias, multiple first pads,and multiple second pads. The intermediate layer has an upper surfaceand a lower surface opposite to each other. The conductive viaspenetrate the intermediate layer and are respectively connected to thefirst pads on the upper surface and the second pads on the lowersurface. The bridge pads are aligned with the upper surface. A firstredistribution structure layer is formed on the upper surface of theinterposer. The first redistribution structure layer is electricallyconnected to the first pads and the bridge pads of the bridge. A secondredistribution structure layer is formed on the lower surface of theinterposer. The second redistribution structure layer is electricallyconnected to the second pads. Multiple chips are disposed on the firstredistribution structure layer. The chips are electrically connected tothe first redistribution structure layer. The chips are electricallyconnected to each other through the bridge.

In an embodiment of the disclosure, the step of embedding the bridge inthe interposer includes the following steps. The bridge is disposed on atemporary substrate. The bridge pads face the temporary substrate. Theintermediate layer is formed on the temporary substrate. Theintermediate layer covers the bridge. The temporary substrate is removedto expose the upper surface of the intermediate layer. Multiple viaspenetrating the intermediate layer are formed. The conductive vias, thefirst pads, and the second pads are formed on the intermediate layer.The conductive vias are respectively located in the vias and connect thefirst pads and the second pads.

In an embodiment of the disclosure, the manufacturing method of thepackage structure further includes the following step. Multiple chippads electrically connected to the first redistribution structure layerare formed on the first redistribution structure layer after forming thefirst redistribution structure layer on the upper surface of theinterposer.

In an embodiment of the disclosure, before disposing the chips on thefirst redistribution structure layer, the manufacturing method furtherincludes the following steps. Multiple copper pillars are respectivelyformed on the chips. Multiple solders are respectively formed on thecopper pillars. The copper pillars are located between the chips and thesolders. The chips are electrically connected to the bridge through thecopper pillars and the solders. Multiple solder balls are formed on thechips. The chips are electrically connected to the first redistributionstructure layer through the solder balls.

In an embodiment of the disclosure, the manufacturing method of thepackage structure further includes the following steps. Multiple solderball pads electrically connected to the second redistribution structurelayer are formed on the second redistribution structure layer afterforming the second redistribution structure layer on the lower surfaceof the interposer. Multiple solder balls are respectively formed on thesolder ball pads.

In an embodiment of the disclosure, the bridge is formed by singulatedcutting of a wafer.

Based on the above, in the design of the package structure of thedisclosure, the bridge having the redistribution circuit layer and thebridge pads is embedded in the interposer, and the bridge pads arealigned with the upper surface of the intermediate layer. Therefore, thefirst redistribution structure layer subsequently formed on theinterposer may have better flatness. In addition, when the chips aresubsequently bonded onto the first redistribution structure layer in aflip-chip manner, each chip may not only be electrically connected to anexternal circuit through the first redistribution structure layer, theinterposer, and the second redistribution circuit layer, two chips mayalso be electrically connected to each other through the bridge, so asto achieve partial or local high-density interconnection. In short, thepackage structure of the disclosure can have better structuralreliability (due to flatness) and chip-to-chip interconnect densities ina way that is cost-effective.

In order for the features and advantages of the disclosure to be morecomprehensible, the following specific embodiments are described indetail in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A to FIG. 1J are schematic diagrams of a manufacturing method of apackage structure according to an embodiment of the disclosure.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

FIG. 1A to FIG. 1J are schematic diagrams of a manufacturing method of apackage structure according to an embodiment of the disclosure. For theconvenience of description, FIG. 1A is shown as a simple top view, andFIG. 1B to FIG. 1J are shown as cross-sectional views.

Regarding the manufacturing method of the package structure of thisembodiment, firstly, please refer to FIG. 1A and FIG. 1B at the sametime. A bridge 110 is provided. The bridge 110 includes a siliconsubstrate 112, a redistribution circuit layer 114, and multiple bridgepads 116. The redistribution circuit layer 114 is disposed on thesilicon substrate 112. The bridge pads 116 are disposed on theredistribution circuit layer 114 and are electrically connected to theredistribution circuit layer 114. Here, the bridge 110 is embodied bysingulated cutting of a wafer 10. The redistribution circuit layer 114is manufactured by adopting a 64-nanometer process technology, thenumber of circuit layers of the redistribution circuit layer 114 is 2layers to 4 layers, and the minimum pitch of the circuit is 0.4 microns.Preferably, the size of the bridge 110 is 3 millimeters times 3millimeters, which means that the size is very small.

Next, please refer to FIG. 1H first. The bridge 110 is embedded in aninterposer 120. The interposer 120 includes an intermediate layer 122,multiple conductive vias 124, multiple first pads 126, and multiplesecond pads 128. The intermediate layer 122 has an upper surface 121 anda lower surface 123 opposite to each other. The conductive vias 124penetrate the intermediate layer 122 and are respectively connected tothe first pads 126 located on the upper surface 121 and the second pads128 located on the lower surface 123. In particular, the bridge pads 116of the bridge 110 are substantially aligned with the upper surface 121of the intermediate layer 122.

In detail, in the step of embedding the bridge 110 in the interposer120, firstly, please refer to FIG. 1C. The bridge 110 is disposed on atemporary substrate 20. The bridge pads 116 face the temporary substrate20. Here, a release film 22 is also disposed on the temporary substrate20. The temporary substrate 20 is, for example, a glass substrate or asteel substrate either round or rectangular structure. The bridge 110 ispositioned on the temporary substrate 20 through the release film 22 ina face-down manner.

Next, please refer to FIG. 1D. The intermediate layer 122 is formed onthe temporary substrate 20. The intermediate layer 122 covers the bridge110. The material of the intermediate layer 122 is, for example, anAjinomoto build-up film (ABF) or an epoxy molding compound (EMC), butnot limited thereto.

Next, please refer to FIG. 1E. The temporary substrate 20 and therelease film 22 are removed to expose the upper surface 121 of theintermediate layer 122.

Next, please refer to FIG. 1F. Through a laser drilling manner, multiplevias 125 penetrating the intermediate layer 122 are formed. The vias 125penetrate the intermediate layer 122 and connect the upper surface 121and the lower surface 123. The vias 125 are located on two sides of thebridge 110.

Next, please refer to FIG. 1G. The intermediate layer 122 is flipped, sothat the upper surface 121 of the intermediate layer 122 faces upward.At this time, the bridge 110 is facing up, and the bridge pads 116 ofthe bridge 110 are still aligned with the upper surface 121 of theintermediate layer 122.

Next, please refer to FIG. 1H. The conductive vias 124, the first pads126, and the second pads 128 are formed on the intermediate layer 122 byelectroplating. The conductive vias 124 are respectively located in thevias 125. Two opposite ends of the conductive via 124 are respectivelyconnected to the first pad 126 and the second pad 128.

Next, please refer to FIG. 1I. A first redistribution structure layer140 is formed on the upper surface 121 of the interposer 120. The firstredistribution structure layer 140 is electrically connected to thefirst pads 126 and the bridge pads 116 of the bridge 110.

Next, please refer to FIG. 1I again. A second redistribution structurelayer 150 is formed on the lower surface 123 of the interposer 120. Thesecond redistribution structure layer 150 is electrically connected tothe second pads 128.

Here, the sequence of forming the first redistribution structure layer140 and the second redistribution structure layer 150 is not limited.For example, the first redistribution structure layer 140 may be formedfirst, and then the second redistribution structure layer 150 may beformed. Alternatively, the second redistribution structure layer 150 maybe formed first, and then the first redistribution structure layer 140may be formed. Alternatively, the first redistribution structure layer140 and the second redistribution structure layer 150 may be formed atthe same time.

After that, please refer to FIG. 1I again. Multiple chip pads 160 areformed on the first redistribution structure layer 140 and areelectrically connected to the first redistribution structure layer 140.Next, multiple solder ball pads 165 are formed on the secondredistribution structure layer 150 and are electrically connected to thesecond redistribution structure layer 150. Afterwards, multiple solderballs 170 respectively are formed on the solder ball pads 165. Here, thesequence of forming the chip pads 160 and the solder ball pads 165 isnot limited.

Finally, please refer to FIG. 1J again. Multiple chips 180 are disposedon the first redistribution structure layer 140. The chips 180 areelectrically connected to the first redistribution structure layer 140.The chips 180 are electrically connected to each other through thebridge 110. Here, the chips 180 may be different forms and types ofchips, which is not limited here. Furthermore, before disposing thechips 180 on the first redistribution structure layer 140, multiplecopper pillars 130 are respectively formed on the chips 180. Then,multiple solders 135 are respectively formed on the copper pillars 130.The copper pillars 130 are located between the chips 180 and the solders135. Then, multiple solder balls 137 are formed on chips 180. The chips180 are electrically connected to the first redistribution structurelayer 140 through the solder balls 137. The chips 180 are electricallyconnected to the bridge 110 through the copper pillars 130 and thesolders 135. So far, the manufacture of a package structure 100 has beencompleted.

In terms of structure, please refer to FIG. 1J again. The packagestructure 100 includes the bridge 110, the interposer 120, the firstredistribution structure layer 140, the second redistribution structurelayer 150, and the chips 180. The bridge 110 includes the siliconsubstrate 112, the redistribution circuit layer 114, and the bridge pads116. The redistribution circuit layer 114 is disposed on the siliconsubstrate 112. The bridge pads 116 are disposed on the redistributioncircuit layer 114 and are electrically connected to the redistributioncircuit layer 114. The interposer 120 includes the intermediate layer122, the conductive vias 124, the first pads 126, and the second pads128. The intermediate layer 122 has the upper surface 121 and the lowersurface 123 opposite to each other. The conductive vias 124 penetratethe intermediate layer 122 and are respectively connected to the firstpads 126 located on the upper surface 121 and the second pads 128located on the lower surface 123. The bridge 110 is embedded in theintermediate layer 122. The bridge pads 116 are aligned with the uppersurface 121. The first redistribution structure layer 140 is disposed onthe upper surface 121 of the interposer 120 and is electricallyconnected to the first pads 126 and the bridge pads 116 of the bridge110. The second redistribution structure layer 150 is disposed on thelower surface 123 of the interposer 120 and is electrically connected tothe second pads 128. The chips 180 are disposed on the firstredistribution structure layer 140 and are electrically connected to thefirst redistribution structure layer 140. The chips 180 are electricallyconnected to each other through the bridge 110.

Furthermore, in this embodiment, the package structure 100 furtherincludes the chip pads 160, the solder ball pads 165, and the solderballs 170. The chip pads 160 are disposed on the first redistributionstructure layer 140 and are electrically connected to the firstredistribution structure layer 140. The chips 180 may be electricallyconnected to the first redistribution structure layer 140 and the bridge110 through the chip pads 160. The solder ball pads 165 are disposed onthe second redistribution structure layer 150 and are electricallyconnected to the second redistribution structure layer 150. The solderballs 170 are respectively disposed on the solder ball pads 165. Thepackage structure 100 may be electrically connected to an externalcircuit (such as a printed circuit board) through the solder balls 170.

In addition, the package structure 100 of this embodiment also includesthe copper pillars 130, the solders 135, and the solder balls 137. Thecopper pillars 130 are respectively disposed on the chips 180. Thesolders 135 are respectively disposed on the copper pillars 130. Thecopper pillars 130 are respectively located between the chips 180 andthe solders 135. The chips 180 are electrically connected to the bridge110 through the copper pillars 130 and the solders 135. The solder balls137 are disposed on the chips 180. The chips 180 are electricallyconnected to the first redistribution structure layer 140 through thesolder balls 137.

In short, in this embodiment, the bridge 110 is first packaged in aface-down manner and is embedded in the interposer 120. After packagemolding the bridge 110, there is no need to adopt polishing and no needto electroplate the copper pillars. Therefore, the package structure 100of this embodiment has the advantages of simple manufacturing processand low cost. Furthermore, since the bridge pads 116 of the bridge 110are aligned with the upper surface 121 of the intermediate layer 122,the first redistribution structure layer 140 subsequently formed on theinterposer 120 may have better flatness. In addition, when the chips 180are subsequently bonded onto the first redistribution structure layer140 in a flip-chip manner, each chip 180 may not only be electricallyconnected to the external circuit through the first redistributionstructure layer 140, the interposer 120, and the second redistributioncircuit layer 150, two chips 180 may also be electrically connected toeach other through the bridge 110, so as to achieve partial or localhigh-density interconnection. In other words, the package structure 100of this embodiment can have better surface flatness and chip-to-chipinterconnect densities in a way that is cost-effective.

In summary, in the design of the package structure of the disclosure,the bridge having the redistribution circuit layer and the bridge padsis embedded in the interposer, and the bridge pads are aligned with theupper surface of the intermediate layer. Therefore, the firstredistribution structure layer subsequently formed on the interposer mayhave better flatness. In addition, when the chips are subsequentlybonded onto the first redistribution structure layer in a flip-chipmanner, each chip may not only be electrically connected to the externalcircuit through the first redistribution structure layer, theinterposer, and the second redistribution circuit layer, two chips mayalso be electrically connected to each other through the bridge, so asto achieve partial or local high-density interconnection. In short, thepackage structure of the disclosure can have better surface flatness andhigher density interconnects that are cost-effective.

Although the disclosure has been disclosed in the above embodiments, theembodiments are not intended to limit the disclosure. Persons skilled inthe art may make some changes and modifications without departing fromthe spirit and scope of the disclosure. The protection scope of thedisclosure shall be defined by the appended claims.

What is claimed is:
 1. A package structure, comprising: a bridge,comprising a silicon substrate, a redistribution circuit layer, and aplurality of bridge pads, wherein the redistribution circuit layer isdisposed on the silicon substrate, and the bridge pads are disposed onthe redistribution circuit layer and are electrically connected to theredistribution circuit layer; an interposer, comprising an intermediatelayer, a plurality of conductive vias, a plurality of first pads, and aplurality of second pads, wherein the intermediate layer has an uppersurface and a lower surface opposite to each other, the conductive viaspenetrate the intermediate layer and are respectively connected to thefirst pads located on the upper surface and the second pads located onthe lower surface, wherein the bridge is embedded in the intermediatelayer, and the bridge pads are aligned with the upper surface; a firstredistribution structure layer, disposed on the upper surface of theinterposer and electrically connected to the first pads and the bridgepads of the bridge; a second redistribution structure layer, disposed onthe lower surface of the interposer and electrically connected to thesecond pads; and a plurality of chips, disposed on the firstredistribution structure layer and electrically connected to the firstredistribution structure layer, wherein the chips are electricallyconnected to each other through the bridge.
 2. The package structureaccording to claim 1, further comprising: a plurality of chip pads,disposed on the first redistribution structure layer and electricallyconnected to the first redistribution structure layer, wherein the chipsare electrically connected to the first redistribution structure layerand the bridge through the chip pads.
 3. The package structure accordingto claim 1, further comprising: a plurality of copper pillars,respectively disposed on the chips; a plurality of solders, respectivelydisposed on the copper pillars, wherein the copper pillars arerespectively located between the chips and the solders, and the chipsare electrically connected to the bridge through the copper pillars andthe solders; and a plurality of solder balls, disposed on the chips,wherein the chips are electrically connected to the first redistributionstructure layer through the solder balls.
 4. The package structureaccording to claim 1, further comprising: a plurality of solder ballpads, disposed on the second redistribution structure layer andelectrically connected to the second redistribution structure layer; anda plurality of solder balls, respectively disposed on the solder ballpads.
 5. A manufacturing method of a package structure, comprising:providing a bridge, comprising a silicon substrate, a redistributioncircuit layer, and a plurality of bridge pads, wherein theredistribution circuit layer is disposed on the silicon substrate, andthe bridge pads are disposed on the redistribution circuit layer and areelectrically connected to the redistribution circuit layer; embeddingthe bridge in an interposer, the interposer comprises an intermediatelayer, a plurality of conductive vias, a plurality of first pads, and aplurality of second pads, the intermediate layer has an upper surfaceand a lower surface opposite to each other, the conductive viaspenetrate the intermediate layer and are respectively connected to thefirst pads located on the upper surface and the second pads located onthe lower surface, and the bridge pads are aligned with the uppersurface; forming a first redistribution structure layer on the uppersurface of the interposer, wherein the first redistribution structurelayer is electrically connected to the first pads and the bridge pads ofthe bridge; forming a second redistribution structure layer on the lowersurface of the interposer, wherein the second redistribution structurelayer is electrically connected to the second pads; and disposing aplurality of chips on the first redistribution structure layer, whereinthe chips are electrically connected to the first redistributionstructure layer, and the chips are electrically connected to each otherthrough the bridge.
 6. The manufacturing method of the package structureaccording to claim 5, wherein the step of embedding the bridge in theinterposer comprises: disposing the bridge on a temporary substrate,wherein the bridge pads face the temporary substrate; forming theintermediate layer on the temporary substrate, wherein the intermediatelayer covers the bridge; removing the temporary substrate to expose theupper surface of the intermediate layer; forming a plurality of viaspenetrating the intermediate layer; and forming the conductive vias, thefirst pads, and the second pads on the intermediate layer, wherein theconductive vias are respectively located in the vias and connect thefirst pads and the second pads.
 7. The manufacturing method of thepackage structure according to claim 5, further comprising: forming aplurality of chip pads electrically connected to the firstredistribution structure layer on the first redistribution structurelayer after forming the first redistribution structure layer on theupper surface of the interposer.
 8. The manufacturing method of thepackage structure according to claim 5, wherein before disposing thechips on the first redistribution structure layer, the manufacturingmethod further comprises: respectively forming a plurality of copperpillars on the chips; respectively forming a plurality of solders on thecopper pillars, wherein the copper pillars are located between the chipsand the solders, and the chips are electrically connected to the bridgethrough the copper pillars and the solders; and forming a plurality ofsolder balls on the chips, wherein the chips are electrically connectedto the first redistribution structure layer through the solder balls. 9.The manufacturing method of the package structure according to claim 5,further comprising: forming a plurality of solder ball pads electricallyconnected to the second redistribution structure layer on the secondredistribution structure layer after forming the second redistributionstructure layer on the lower surface of the interposer; and respectivelyforming a plurality of solder balls on the solder ball pads.
 10. Themanufacturing method of the package structure according to claim 5,wherein the bridge is formed by singulated cutting of a wafer.